Semiconductor device and method for fabricating the same

ABSTRACT

Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. Ser. No. 10/625,277, entitled“Semiconductor Device and Method for Fabricating the Same”, filed onJul. 23, 2003, the contents of which are expressly incorporated byreference herein in its entirety for all purposes.

1. Technical Field

A semiconductor memory device is disclosed that includes a lowerelectrode for a capacitor. A method for fabricating the same is alsodisclosed.

2. Description of Related Art

Recently, a variety of technologies for improving charge storagecapacity has been developed as the size of semiconductor devices isreduced. As a preferable choice, the capacitor has been formed as athree-dimensional (3D) structure. For example, a concave capacitor is arepresentative capacitor having the 3D structure.

FIGS. 1A to 1C are cross-sectional views showing a conventional methodfor fabricating a semiconductor device that includes a lower electrode.

As shown in FIG. 1A, a first insulation layer 11 that is an oxide basedlayer is formed over a semiconductor substrate 11. A first plug 12 isformed to be in contact with the semiconductor substrate 10 bypenetrating the first insulation layer 11. The first plug gets to be incontact with an impurity diffusion area such as a source/drain region.

Herein, a tetra-ethyl-ortho-silicate (TEOS) material is used for formingthe first insulation layer 11. In addition, the first plug 12 is formedwith a poly-silicon material. Furthermore, to prevent a diffusion of anohmic contact material and lower electrode material into thesemiconductor substrate 10, a barrier layer with a Ti/TiSi2/TiNstructure (not shown) is usually formed over the first plug 12.

A planarizaiton process, so called a chemical mechanical polishing (CMP)process, is carried out to planarize an upper part of a layer comprisingthe first plug 12 and first insulation layer 11, and a second insulationlayer 13 is formed over the planarized layer.

Bit lines 14 are formed on the second insulation layer 13. Herein, thebit lines 14 should not be over lapped with the first plug 12. Inaddition, a first etch stop layer 15 constituted with one of nitridebased layers is thinly formed along an entire upper profile of thesubstrate.

The first etch stop layer 15 prevents losses of the bit lines 14 duringa succeeding etching process for forming a storage node contact.Especially, a nitride based layer such as a silicon nitride layer or asilicon nitride oxide layer is used to obtain an etching selectivity toa third insulation layer 16 which is also an oxide based layer.

The third insulation layer 16 is thickly deposited over the first etchstop layer 15. Continuously, another planarization process is carriedout to planarize an upper part of the third insulation layer 16 by usingan etch-back method or the CMP process.

Next, a photo-resist pattern 17 for forming a storage node contact isformed.

In addition, a capacitor contact hole exposing the first plug 12 isformed by sequentially etching the third insulation layer 16, the firstetch stop layer 15 and the second insulation layer 13 even if thecapacitor contact hole is not illustrated. Herein, the photo-resistpattern 17 is used as an etching mask.

At this time, the third insulation layer 16 is etched through a firstetching process and the first etching process stops before the firstetch stop layer 15 is etched. Thereafter, the first etch stop layer 15and the second insulation layer 11 are then etched through a secondetching process again. A required etching profile can be obtained byvarying an etching recipe for each of the first and second etchingprocesses.

The capacitor contact hole is stuffed with a plug material such as apoly-silicon while the plug material is deposited over an entire upperpart of the substrate. As a result, a second plug is formed andelectrically gets to be in contact with the first plug. Another CMPprocess is carried out to perform a planarization process for an upperpart of the semiconductor substrate which has gone through thepredetermined processes.

Next, a second etch stop layer 19 that is a nitride based layer isformed to prevent the second plug 18 from being attacked during anetching process for a lower electrode which will be formed through asucceeding process. Continuously, a sacrifice insulation layer 20constituted that is an oxide based layer is formed after determining thevertical height of the capacitor which will be formed over the secondetch stop layer. The oxide layer used for forming the sacrificeinsulation layer 20 can affect a capacity of the capacitor which will beformed. Next, another photo-resist pattern 21 is formed.

Herein, an extra process for forming the second etch stop layer could beskipped because the etching process for forming the lower electrode canbe easily controlled.

The photo-resist pattern 21 used for etching the sacrifice insulationlayer 20 is shown in FIG. 1B.

The photo-resist pattern 21 serves as an etching mask used for etchingthe sacrifice insulation layer 20.

The etching process for removing the sacrifice insulation layer iscarried out. Herein, the etching process is held back by the second etchstop layer 19 once and then, begins to be carried out again. The secondetch stop layer is also removed thereafter.

As a result, an open part, i.e., an exposed surface of the second plug18 is formed.

After removing the photo-resist pattern 21, a conductive material forthe lower electrode is formed along a whole surface with an open partformed by etching the sacrifice insulation layer 20. Consequently, thesecond plug 18 gets to be in contact with the conductive material.

Next, the photo-resist is deposited over the entire surface with theopen part in order to cover the entire surface. Next, the entire surfaceof the substrate covered with the photo-resist is planarized byperforming the etch-back process or the CMP process until the sacrificeinsulation layer is exposed.

The exposed sacrifice insulation layer mentioned above is removed by awet dip-out process using a buffered oxide etchant (BOE) or a hydrogenfluoride (HF) acid. Consequently, a lower electrode 22 with a concavestructure shown in FIG. 1C is formed.

Continuously, a remnant photo-resist is removed by carrying out a drystrip process. At this time, O2/CF4/H2O/N2 or O2/N2 is used for the drystrip process. Also, a solvent is used to clearly remove the remnantphoto-resist and by-products generated during a cleaning process using asolvent.

As a next step, a heat treatment process is performed to recover adegraded property of the lower electrode 22 caused by the etchingprocess. An extra cleaning process for removing remnant impurities iscarried out by using the BOE prior to forming a dielectric layer.

Even though not illustrated, the capacitor is completely formed afterforming the dielectric layer and a upper electrode over the lowerelectrode 22.

FIG. 2 is a top view illustrating a plurality of conventional lowerelectrodes.

For reference, FIG. 2 shows a two dimensional arrangement for theconventional lower electrodes.

Referring to FIG. 2, a plurality of lower electrodes 22 is arranged inone direction, and a plurality of second plugs 18 are disposed onbetween bit lines arranged in a matrix distribution. Each of the secondplugs 18 is over-lapped to the adjacent second plug 18. Also, aplurality of lower electrodes 22 are disposed to be in contact with thesecond plugs 18, respectively.

Until recently, a mask pattern of a quadrilateral shape or an ellipticalshape with a high ratio of a major axis and a minor axis is used to etchthe sacrifice insulation layer 20. As a result, a concave, type or acylinder type of a lower electrode 22 pattern is formed. Concerning themask pattern with an ellipse shape, its original plane feature is notthe ellipse shape but a quadrilateral shape. The quadrilateral shape ischanged to the ellipse shape after the etching process is carried out.

During the lower electrode 22 pattern formation, a leaning phenomenon ofthe lower electrode 22 takes place because of a surface tension of theHF acid or the BOE. Herein, the HF acid or the BOE is used to perform adip-out process of the sacrifice insulation layer 20 for forming thelower electrode 22 shown in FIG. 1C. Furthermore, an electrical short ofneighboring lower electrodes is caused by the leaning phenomenonmentioned above.

FIG. 3 is a cross-sectional view illustrating an electrical short of theneighboring lower electrodes. As the semiconductor device gets highlyintegrated, a distance between the neighboring lower electrodes getsnarrower and thereby, frequently causing the leaning phenomenonillustrated in FIG. 3.

Accordingly, a line width of the lower electrode 22 becomes finer andtherefore, the electrical short of the neighboring lower electrodestakes place more frequently.

The lower electrodes of the cylinder type capacitor has been arranged inthe matrix distribution. The lower electrodes in accordance with animproved prior art are disposed in a zigzag distribution. Herein, twoadjacent lower electrodes which are located at both sides of the bitline become a pair and each of the paired electrodes is disposed in away that one of the paired lower electrodes is disposed ahead of theother in the X-axis imaginary line. Consequently, the lower electrodesare disposed in the aforementioned zigzag distribution.

As a result, a partial confrontation area, which is formed when thepaired lower electrodes face each other in an opposite direction, isreduced and the aforementioned electrical short between the lowerelectrodes is prevented.

FIG. 4 is a top view of the semiconductor device including the lowerelectrodes in accordance with the improved prior art.

Referring to FIG. 4, a plurality of bit lines are formed in anX-direction. A plurality of X virtual axis having a direction, which isidentical to the X-direction, and a plurality of Y virtual axis having adirection, which is vertical to the X-direction, are shown in FIG. 4.Herein, only two X virtual axis and only two Y axes imaginary lines,that is, X1 and X2, and Y1 and Y2 are shown in FIG. 4. Also, more Y-axisimaginary lines Y1′, Y1″, Y2′, Y2″ are shown in FIG. 4.

The X virtual axis (X1, X2) and the Y virtual axis (Y1, Y2) cross eachother and thus, a matrix structure or lattice structure having aplurality of inter-section points is obtained. Herein, midpoints of aplurality of capacitor plugs 41 are located at the inter-section points,and therefore, the capacitor plugs 41 are disposed in the matrixdistribution.

More specifically, the capacitor plugs 41 are connected with the firstplugs, which are in contact with an activation area of the semiconductorsubstrate. In addition, the capacitor plugs 41 are disposed within apredetermined interval ‘d2’, and the capacitor plugs 41 neighboring inthe Y-direction are formed within a predetermined distance ‘d1’, whichis same as a width of the bit line 40.

Each upper area of the capacitor plugs 41 is electrically connected witheach lower electrode 42 in one-to-one correspondence, and the lowerelectrodes 42 neighboring in the X-direction within a predeterminedinterval d3.

Herein, along a Y virtual axis selected at discretion, for example, Y1which passes through a midpoint of the capacitor plug 41, a pair oflower electrodes 42A and 42B neighbors each other and the paired lowerelectrodes are disposed on different but neighboring X virtual axis.Furthermore, as shown in FIG. 4, one of the paired lower electrodes 42Aand 42B is disposed ahead of the other in view of the X-imaginary line.

Consequently, even if not illustrated, the interfacial tension caused bya wet etching solution used to remove a sacrifice insulation layer byperforming the dip-out process after forming the lower electrode 42 isreduced by the zigzag distribution of the lower electrodes and thereby,the electrical short between the neighboring lower electrodes can beprevented by the above-mentioned arrangement for the lower electrodes42.

However, as the semiconductor device is highly integrated, a drawbacksuch as a reduced process margin required for securing a contact areafor a plug still exists.

Such drawback as mentioned above still remains in the semiconductordevices conventionally fabricated.

The leaning phenomenon caused by the wet dip-out process for thesacrifice insulation layer is somewhat prevented by arranging the lowerelectrodes in the zigzag distribution. However, a problem with themethod mentioned above still exists as the photo-resist pattern becomesextremely fine, and therefore, the separation distance between the lowerelectrodes gets closer.

In addition, the electrical short between the neighboring lowerelectrodes is generated by a lift of a lower electrode. Herein the liftof the lower electrode is one of causes collapse of the photo-resistpattern.

An etching process is performed along the major axis is different froman etching process is performed along the minor axis when thesacrificial insulation layer is a rectangular or elliptical shape havinga high ratio of a major axis to a minor axis. As a result, an etchingprofile, which generates a tapering feature, is generated at the majoraxis, and therefore, an effective area for forming the lower electrodeis reduced. Therefor, effective area for forming the capacitor is alsoreduced.

In addition, compared with a critical dimension of an upper plane of thestructure mentioned above, that of a lower plane is reduced. Therefore,a bump such as a meta-stable poly silicon (MPS) used for increasing thecapacitance can not be formed due to a short between bumps formed at thebottom plane of the lower electrode. Furthermore, a dielectric layer andthe lower electrode can not be formed due to the short between thebumps.

FIGS. 5 (A) and (B) are schematic cross-sectional views of the lowerelectrode shown along an Y1″ imaginary line and the X1 imaginary lineshown in FIG. 4.

In short, FIGS. 5, (A) and (B) are cross-sectional views of the lowerelectrode shown along the major axis of the ellipse shape and the minoraxis of the ellipse shape, respectively.

As already mentioned, the cylinder type capacitor has the quadrilateraland the ellipse shape. In addition, an aspect ratio of the major axisand the minor axis is extremely high because the etching process iscarried out mainly along the minor axis.

The etching profiles for the major axis and the minor axis are notidentical due to different etching properties which are very sensitiveto the aspect ratio. Therefore, because of the etching properties of thesacrifice insulation layer, a vertical etching profile as indicated by areference mark ‘45’ in FIG. 5 (B) is obtained along the minor axis andthe tapering etch profile as indicated by a reference mark ‘44’ in FIG.5 (A) is obtained along the major axis. Such tapering etch profilecauses a decrease in the effective capacitance. In addition, thecapacitance is further decreased because the bump can not be formed dueto a short between bumps at the lower plane of the lower electrode asmentioned.

The other hand, an excessive etching process along the major axis may becarried out to obtain a vertical etch profile. In this case, thesacrifice insulation layer is over etched along the minor axis though.Consequently, a “bowing” profile is obtained by the excessive etchingprocess mentioned above. Such a bowing profile also becomes anothercause inducing the short between the lower electrodes as already shownin FIG. 3.

In addition, a possibility of the lower electrode being lifted duringthe dip-out process or other succeeding processes is increased by areduced contact area of the lower electrode. Herein, the contact area isreduced by the tapering etch profile formed along the major axis.Furthermore, a thickness of the deposited lower electrode is decreaseddue to a narrow critical dimension and thereby, increasing a possibilityof the lower electrode being eventually broken.

As size of semiconductor devices is decreased, an etching depth forsecuring a constant capacitance gets deeper and thereby, increasing theaspect ratio gradually. In addition, a difference between etchingprofiles formed along the major axis and the minor axis becomes morepronounced. Consequently, an effective capacitor area is reduced and itbecomes difficult to secure the required capacitance. Furthermore, apossibility that an electrical short is generated by a bridgingphenomenon is substantially increased.

SUMMARY OF THE DISCLOSURE

A semi-conductor device is disclosed that is capable of preventing ashort of lower electrodes caused by a leaning or lifting phenomenonduring processes for forming the lower electrodes and while stillproviding enough capacitance by widening an effective capacitor area. Amethod for fabricating the same is also disclosed.

A disclosed semiconductor device comprises a plurality of capacitorplugs disposed in an orderly separation distance, wherein midpoints ofthe capacitor plugs are located at inter-section points of X virtualaxis and Y virtual axis which are vertical to the X virtual axis; and aplurality of lower electrodes used for a capacitor and disposed in anorderly separation distance to be respectively connected with thecapacitor plugs, wherein midpoints of paired lower electrodes coupledalong a Y virtual axis are respectively located at different positionsdeviated from the Y virtual axis in opposite direction along thedifferent X virtual axis and an upper plane of the lower electrodefeatures an octagonal or a circular shape.

BRIEF DESCRIPTION OF THE DRAWINGS

Other aspects of the disclosed devices and methods will become apparentfrom the following description of the preferred embodiments withreference to the accompanying drawings, wherein:

FIGS. 1A to 1C are cross-sectional views illustrating a process forforming a lower electrode of a conventional semiconductor device;

FIG. 2 shows a top view of a plurality of lower electrodes;

FIG. 3 is a schematic cross-sectional view illustrating an electricalshort caused by a leaning phenomenon between lower electrodes;

FIG. 4 is a top view showing a conventional semiconductor deviceincluding a plurality of lower electrodes with the prior art;

FIG. 5 is schematic cross-sectional views of a lower electrode shownalong an Y1″ imaginary line and an X1 imaginary line in FIG. 4,respectively.

FIG. 6 is a schematic top view of a semiconductor device including alower electrode formed in accordance with a first disclosed embodiment;

FIG. 7 is a cross-sectional view of a lower electrode shown along an X1imaginary line, an Y1″ imaginary line, and a Z-Z′ line in FIG. 6;

FIG. 8 is a perspective views of lower electrodes having an octagonal ora circular cylinder structure;

FIG. 9 is a schematic cross-sectional view of a semiconductor deviceincluding lower electrodes in accordance with a second disclosedembodiment;

FIGS. 10 to 12 are schematic top views illustrating semiconductordevices including lower electrodes formed in accordance withrespectively different arrangements;

FIG. 13 is a top view showing an example of a disclosed mask pattern;

FIGS. 14A to 14D are cross-sectional views showing processes forfabricating a semiconductor device using a contact pad in accordancewith another disclosed embodiment;

FIG. 15 is Transmission Electron Microscope (TEM) pictures showing aleaning phenomenon occurring between lower electrodes; and

FIG. 15 is TEM pictures illustrating a disclosed lower electrodepattern.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Hereinafter, semiconductor device is disclosed that is capable ofpreventing electrical shorts of lower electrodes caused by a leaning orlifting phenomenon during forming the lower electrodes and whichprovides enough capacitance by widening an effective capacitor area.Methods for fabricating the same will also be described in detailreferring to the accompanying drawings.

FIG. 6 is schematic top view showing semiconductor devices including alower electrode formed in accordance with a first disclosed embodiment.

Referring to FIG. 6, a plurality of bit lines 60 are formed in an Xdirection. A plurality of X virtual axis (only X1 and X2 are illustratedin FIG. 6) having a direction identical to the X direction and aplurality of Y virtual axis (only Y1 and Y2 are illustrated in FIG. 6)vertical to the X virtual axis are illustrated in FIGS. 6A and 6B. Also,four more Y virtual axis Y1′, Y1″, Y2′ and Y2″ are illustrated in FIG.6.

A matrix structure is formed with the X virtual axis and the Y virtualaxis, and accordingly, a plurality of inter-section points is formed. Aplurality of capacitor plugs 61 is formed as interleaved between the bitlines. More particularly, the capacitor plugs are formed as a midpointof the capacitor plug to be located at the inter-section point and inbetween bit lines.

In detail, the capacitor plug 61 is connected with a first plug which isin contact with an activation area, i.e., a source/drain region, of asemiconductor substrate. In addition, the capacitor plugs 61 neighboringalong the X virtual axis are formed within a predetermined interval‘d2’. In view of the Y virtual axis, the capacitor plugs 61 are formedwithin a predetermined interval ‘d1’ which is identical to a width ofthe capacitor plug 61 or the bit line 60. For reference, the width ofthe capacitor plug 61 is identical to that of the bit line 60.

However, a distance between the neighboring capacitor plugs is smallerthan the ‘d1’ and the ‘d2’ in reality because a landing plug structureis adopted for form the capacitor plug 61. Herein, describing thelanding plug structure, an upper plane of the capacitor plug 61 isminimized to satisfy a technical progress toward a large-scaleintegration, and a lower plane of the capacitor plug 61 becomes widerthan the upper plane.

Each of the upper planes of the capacitor plugs 61 is electricallyconnected with corresponding lower electrode 62 in one to onecorrespondence, and the lower electrodes 42 neighboring along the Xvirtual axis are formed in a predetermined interval ‘d3’.

Herein, along a Y virtual axis selected at discretion, for example, Y1which passes through a midpoint of the capacitor plug 61, a pair oflower electrodes 62A and 62B neighbors to each other, and the pairedlower electrodes are located at different X virtual axis. Herein, thepaired lower electrodes are formed to have an area that the lowerelectrodes 62 face each other in opposite direction are minimized orzero. That is, the paired lower electrodes are formed not to beoverlapped to have overlapped in minimum, if the paired lower electrodesare on same X virtual axis. Therefore, the distance of two neighbored Yvirtual axis has to be controlled in order to optimize an interval ofthe paired lower electrodes.

As shown in FIG. 6, both of midpoints of the capacitor plugs which arein contact with the lower planes of the lower electrodes 62A and 62B arelocated on one Y virtual axis (Y1). However, the midpoints (01′, 01″) ofthe lower electrodes are located on different Y virtual axis (Y1′, Y1″),respectively.

In short, each of the paired lower electrodes 62A and 62B is formed oncorresponding X virtual axis (X1, X1) and on different Y virtual axisnot to be overlapped or to be overlapped in minimum, if the paired lowerelectrode is on same X virtual axis.

Thus, the lower electrodes 62 formed in a zigzag distribution arehelpful for reducing the area that the lower electrodes face each otherin opposite direction. In addition, an interfacial tension caused by asolution used for a wet dip-out process for removing a sacrificeinsulation layer after forming the lower electrode 62 can be reduced.For reference, the sacrifice insulation layer is not illustrated.Consequently, an electrical short of the lower electrodes caused by thelifting phenomenon can be prevented.

In addition, if one of the paired lower electrodes 62 may be located atan area indicated by a reference mark ‘d2’, it is possible to make thearea the paired lower electrodes facing each other in opposite directiondisappear. In the case mentioned above, size of the lower electrode 62can be increased and thereby, also increasing the capacitance of thecapacitor.

Consequently, the lower electrodes deposited in the zigzag distributionare helpful for preventing a bridge phenomenon. Furthermore, a moreeffective method for solving the bridge phenomenon generated between thelower electrodes can be suggested. The capacitor plugs themselves may bedisposed in a zigzag distribution. In this case, the bridge phenomenoncan be considerably reduced.

A reduction of the capacitance of the capacitor caused by differentetching profiles of a major and a minor axis of the sacrifice insulationlayer is avoided, and a bowing profile formation of the sacrificeinsulation layer caused by an excessive etching process along the minoraxis is also prevented. The budging phenomenon is also alleviated.

According to a first disclosed embodiment, upper planes of a pluralityof lower electrodes 62 are formed to have an octagonal or circularshape. The major and minor axes of the upper plane can not be defined.Furthermore, although the octagonal or circular shape is non-symmetricaland there exist the major and minor axes, the aspect ratio, that is, theratio of the major axis to the minor axis merely ranges from about 1 to1 to about 2 to 1. Consequently, a trade-off problem of the capacitancereduction and the electrical short between the lower electrodes can besolved concurrently.

Herein, the lower electrode 62 having the aspect ratio of 1 to 1 isregarded as a most ideal case.

FIGS. 7 (A) (B) (C) are schematic cross-sectional views of the lowerelectrode 62 respectively shown along an X1 imaginary line, an Y1″imaginary line and a Z-Z′ imaginary line shown in FIG. 6. When the lowerelectrodes 62 having octagonal or circular cylinder structure areapplied to the semiconductor device, the capacitance of the capacitorcan be improved and the bowing phenomenon of the sacrifice insulationlayer caused by an excessive etching process is prevented because theaspect ratio of the major and minor axes of the lower electrodes 62having the octagonal or circular cylinder structure is about 1 to 1

In addition, the area that the paired lower electrodes face each otherin opposite direction can be reduced by disposing the lower electrode 62in the zigzag distribution. Herein, the lower electrode is located at anarea corresponding to between the bit lines. Consequently, the bridgephenomenon of the lower electrodes caused by the interfacial tension ofa wet etching solution can be prevented, wherein the wet etchingsolution is used for removing a remnant sacrifice insulation layer bycarrying out a wet dip-out process. In addition, an area occupied by thelower electrode 62 can be much more increased by disposing the pairedlow electrodes in the zigzag distribution and thereby, increasing thecapacitance of the capacitor.

Furthermore, as a difference of the etching profiles along the majoraxis and the minor axis becomes considerably smaller, an upper planearea of the lower electrode 62 and a lower plane area of the lowerelectrode 62 become practically same after carrying out a chemicalmechanical polishing (CMP) process for planerizing a surface of thesemiconductor device which has gone through predetermined processes.Eventually, the lower electrode with the octagonal or circular cylinderstructure is formed. At this time, a lateral plane of the lowerelectrode is vertical to both of the upper plane and the lower plane.

FIG. 8 is a perspective view of the lower electrodes with athree-dimensional octagonal or circular cylinder structure. Referring toFIG. 8, it is shown that the upper plane A area is practically identicalto the lower plane B area, and the lateral place C is vertical to bothof the upper plane A and the lower plane B.

Therefore, a critical dimension ‘CD1’ of the lower plane B of the lowerelectrode 62 is practically identical to another critical dimension‘CD2’ of the upper plane A of the lower electrode 62 and thereafter, ameta-stable poly silicon (MPS) layer can be grown on the electrode layer62, and a dielectric layer can be grown on the MPS layer after formingthe MPS layer, successively. In addition, an increased volume of thelower electrode with the octagonal or circular cylinder structureincreases the capacitance of the capacitor as well.

Furthermore, it is possible to form the lower electrode 62 withconsiderably thick thickness, and a contact area of the lower plane isalso increased.

The lower electrode can be formed by using the capacitor plug layoutidentical to that in accordance with the prior art without performingadditional processes any more.

FIG. 9 shows schematic cross-sectional views of the semiconductor deviceincluding the lower electrode in accordance with the second disclosedembodiment.

Referring to FIG. 9, a plurality of bit lines are formed in thedirection of the X virtual axis, and the capacitor plugs 61 arerespectively disposed between the bit lines. Herein, a whole layout ofthe disposed lower electrodes 62 shows a same matrix distribution asalready described in FIG. 6.

However, according to the second embodiment, a plurality of contact pads63 are used to connect the lower electrode 62 with the capacitor plug 61electrically. To form the contact pad, an extra process is required.However, if the contact pad 63 is applied to the semiconductor device, acontact area of the contact pad 63 is increased. However, the area thatthe lower electrodes 62 face each other in opposite direction areminimized or even become zero. Herein, the lower electrodes 62, forexample, the paired lower electrodes 62A and 62B are located at bothsides of the bit line 60.

As shown in FIG. 9, only along the X virtual axis indicated with areference mark ‘ROW1’ the contact pads 63 are formed. Also, the midpointof the contact pad 63 is located at the X virtual axis X1 and the Yvirtual axis Y1′. In short, in view of the Y virtual axis, the contactpad 63 is shifted from the Y virtual axis Y1 to the Y virtual axis Y1″.Above-described structural feature is applied to whole layout of thecontact pads 63 distribution.

In addition, as described in the first embodiment, the lower electrodes62 are formed in the zigzag distribution and thereby, decreasing thearea that the paired lower electrodes face each other.

Consequently, the lifting phenomenon of the lower electrode 62 and theelectrical short between the lower electrodes 62 can be considerablyreduced or prevented. Also, the pattern collapse phenomenon is preventedby the octagonal or circular shape of the upper plane of the lowerelectrode 62 and thereby, increasing the capacitance of the capacitor.

In addition, a contact resistance is also decreased by widening an areaof which the contact pad is applied to make the capacitor plug 61 be incontact with the lower electrode 62.

In FIGS. 10 and 11, the contact pads 63 are formed along all X virtualaxis.

In FIG. 12, the contact pads are formed only along the X virtual axiscorresponding to a line indicated with the reference mark ‘ROW2’,

Referring to FIG. 12, the contact pads 63 are formed along the Ximaginary line indicated with the reference mark ‘ROW2’, that is, the X2axis imaginary line. The midpoint of the contact pad 63 is shifted in aright direction.

In view of a process margin, the contact pad 63 is much moreadvantageous than the capacitor plug 61. As a result, the contact pads63 with sufficiently large size can be easily applied to a semiconductordevice fabrication.

Referring to FIG. 10, the contact pads 63 are formed along all of the Xvirtual axis, and upper plane size of the contact pad 63 is larger thanthat of the capacitor plug 61.

Also, a contact area between the lower electrode 62 and the contact pad63 is increased, and another contact area between the lower electrode 62and the capacitor plug 61 is also increased. Consequently, an over-lapmargin and the contact resistance are decreased.

Referring to FIG. 11, the contact pads 63 are disposed along all Xvirtual axis. Furthermore, the contact pads 63 are disposed in thezigzag distribution wherein the zigzag distribution has been alreadydescribed to explain the distribution of the lower electrodes 62 asshown in FIG. 6.

Also, in FIGS. 10 and 11, the areas that the paired lower electrodes,for example, 62A and 62B, face each other in opposite direction areminimized.

Below, it will be explained that problems caused by the wet dip-outprocess for the sacrifice insulation layer can be overcome through thefirst and second embodiments.

Specifically, FIG. 13 is a top view showing an example for a maskpattern. Describing the first embodiment shown in FIG. 6, the area thatthe paired lower electrodes face each other opposite direction isminimized or become zero by locating the midpoints of the paired lowerelectrodes 62 in the zigzag distribution along the X virtual axis. InFIG. 13, an open part 130 of the mask pattern is used to form the pairedlower electrodes. In short, the mask pattern capable of realizing theabove-mentioned distribution of the paired lower electrodescorresponding to the open part of the mask pattern is shown in FIG. 13.The specific process for forming the lower electrodes by using the maskpattern will now be described.

FIG. 13 shows the electrode mask pattern for forming the distribution ofthe lower electrodes shown in FIGS. 6A and 6B.

Midpoints of the open parts are located at Y1′ imaginary line and the Y″imaginary line as shown in FIG. 13. Consequently, an area that the openparts 130 face each other in opposite direction becomes zero. Herein areference mark 131 indicates an area not being opened, that is, aremnant sacrifice insulation layer area.

The open part of the mask pattern has a quadrilateral shape. However,the lower electrodes in accordance with the first embodiment and thesecond embodiment have the octagonal or circular shape. Such phenomenonis caused by a characteristic etching mechanism occurring around acorner are of the quadrilateral shape while performing an etchingprocess.

Furthermore, to obtain the upper planes of the lower electrodes with theoctagonal or circular shape, a mask pattern with the open part with asquare shape is preferred over a mask pattern with the open part havinga rectangular shape.

Also, a mask pattern comprising the open part featured by the octagonalshape is used to obtain the octagonal or circular shapes.

FIGS. 14A to 14D are cross-sectional views showing fabrication processesfor the semiconductor device with a contact pad.

A first insulation layer 141 comprising an oxide based layer is formedover a substrate comprising various elements for fabricating thesemiconductor device such as a transistor. Next, the first insulationlayer 141 is penetrated to form a first plug 142. At this time, the 1stplug 142 is electrically connected to an impurity diffusion area such assource/drain area formed the substrate 140.

Herein, a TEOS layer is used for the for insulation layer 141. The firstplug 142 is poly-silicon. A barrier layer with a structure such asTi/TiSi2/TiN or Ti/TiN is formed over the first plug 142 in order toprevent a diffusion of an ohmic contact and a lower electrode materialinto the substrate even if not illustrated.

A planerization process such as a chemical mechanical process (CMP) iscarried out to planerize the first plug 142 and the first insulationlayer 141 and thereafter, forming a second insulation layer over theplanerized structure.

Next, a bit line 144 is formed over the second insulation layer 143. Atthis time, the bit line is not over-lapped with the first plug 142. Afirst etch stop layer 145 constituted with a nitride based layer isthinly formed along an entire profile comprising the bit line 144.

The first etch stop layer 145 is used to prevent loss of the bit line144 during an etching process for forming a lower electrode contact.Especially, a nitride based layer such as a silicon nitride layer orsilicon oxide nitride layer is used to obtain an etching selectivity ofa third insulation layer 146 constituted with an oxide based layer.

The third insulation layer 146 constituted with an oxide based layer isthickly formed over the first etch stop layer 145 and an upper plane ofthe substrate which has gone through the predetermined processes isplanerized by performing a blanket etching process or the CMP process.

Continuously, the third insulation layer 146, the 1st etch stop layer145, and the second insulation layer 143 are sequentially etched byusing a photo-resist pattern 147 and thereafter, forming a contact holewhich exposes the first plug 142 even if not illustrated.

At this time, a first etch stop is required prior to etching the firstetch stop layer 145 and thereafter, the first etch stop layer 145 andthe second insulation layer 143 are etched again. Eventually, theetching profile having the vertical structure is obtained.

Continuously, a conductive material such as poly-silicon is deposited onthe entire surface of the substrate which has gone through thepredetermined processes in order to bury the contact hole, and anotherCMP process is performed to planerize the substrate. Herein, the secondplug 148 may be regarded as a main capacitor plug because the lowerelectrode of the capacitor and the first plug 142 are electricallyconnected by the second plug 148.

As a next step, a second etch stop layer 149 constituted with a nitridebased layer is formed to prevent an attack to the second plug 148 duringa succeeding etching process for forming the contact pad. However, it ispossible to skip the process for forming the second etch stop layerbecause succeeding etching processes for forming the lower electrode ofthe capacitor lower electrode can be easily controlled.

Next, a fourth insulation layer constituted with an oxide based layer isformed over the second etch stop layer 149. At this time, an upper planeof the fourth insulation layer 150 becomes planerized because an oxidelayer having excellent flatness is used or an extra planerizaitonprocess is carried out.

Continuously, a mask pattern 151 used to form the contact pad is formedover the fourth insulation layer 150.

At this time, as suggested by the first and second embodiments, the maskpattern 151 includes the paired open parts that are adjacent to eachother and located along the Y virtual axis. In addition, the area thatthe open parts 130 face each other in opposite direction is minimized orbecomes zero. In short, the open parts 130 are disposed in the zigzagdistribution in view of entire layout. At this time, the area that theopen parts face each other in opposite direction corresponds to thepaired portions of the sacrifice insulation layers formed by using themask pattern 151 comprising the paired open parts 130.

In addition, at least one of the paired open parts 130, morespecifically, the midpoint of at least one of the paired open parts 130is located at a position deviated from the Y virtual axis along the Xvirtual axis, or the midpoints of the open parts are respectivelylocated at different positions deviated from the Y virtual axis inopposite direction along the X virtual axis.

FIGS. 14A to 14D show a procedure for fabricating the semiconductordevice as an example explaining a fact that size of the contact pad 152is larger than that of the capacitor plug 148.

The open part which is not illustrated is formed by etching the fourthinsulation layer 150 and the etch stop layer 149. At this time, the maskpattern 151 is used as an etching mask. Next, a material used forforming the contact pad 151 used to connect the capacitor plug 148 withthe lower electrode electrically is formed and thereafter, carrying outthe CMP process to planerize the contact pad 152. In addition, a thirdetch stop layer 153 constituted with a nitride based layer is formedover the contact pad 152 for the purpose of preventing loss of thecontact pad 152 caused by the etching process of the sacrificeinsulation layer for forming the lower electrode.

FIG. 14C is a cross-sectional view showing the third etch stop layer 153formed on the contact pad 152.

Herein, it is possible for the contact pad 152 to have plane structuresshowing a variety of shapes such as an octagonal shape, a circularshape, an ellipse shape, a quadrilateral shape, triangular shape and soon.

Instead of depositing the material used for forming the contact pad 152and planerizing it after forming the fourth insulation layer 150 andpattering it as already mentioned, the material for forming the contactpad 152 may be deposited over the second plug 148 directly and patternedto form the contact pad 152.

The sacrifice insulation layer is an oxide layer affecting thecapacitance and is formed considering a vertical height of the capacitoron the third etch stop layer 153. Herein, the sacrifice insulation layeris not illustrated. Next, the mask pattern for forming the lowerelectrode is formed, wherein the mask pattern is not illustrated.

At this time, the midpoint of the lower electrode is not located exactlyat the midpoint of the capacitor plug 148, and the photo-resist patternshould be appropriately controlled so as to maximize an area where thelower electrode and the contact pad are in contact with each other.

The sacrifice insulation layer is etched by using the mask pattern. Atthis time, the etching process if held back by the third etch stop layer153 once, and thereafter removing the third stop layer in order to formthe open part exposing a surface of the contact pad 152.

After removing the mask pattern, a conductive layer used for thecapacitor lower electrode is deposited to be connected with the contactpad 152 along a profile obtained by the sacrifice insulation layer beingetched and opened, that is, an entire profile comprising the open part.Next, the photo-resist is deposited enough to bury the formed conductivelayer comprising a concave structure, and the conductive layer isplanerized and isolated by carrying out the blanket etching process orCMP process until the surface of the sacrifice insulation layer isexposed.

Continuously, as shown in FIG. 14D, the lower electrode 154 structurewith a concave shape is formed by removing a remnant sacrificeinsulation layer by performing the wet dip-out process using a solutionmixed with BOE and HF, or H2SO4 and H2O2. For reference, a ratio of theBOC or HF, and H2SO4 or H2O2 is about 4 to 1.

Consequently, an area that the paired lower electrodes face each otherin opposite direction is reduced by the aforementioned mask pattern.Herein, the paired lower electrodes are located at both sides of the bitline. As a result, the interfacial tension is reduced by the wet etchingsolution used during the wet dip-out process, and the electrical shortof the lower electrodes caused by the lifting phenomenon can beprevented.

Also, a reduction of the capacitance of the capacitor by the differentetching properties of the major axis and the minor axis can beminimized. Furthermore, the leaning phenomenon of the lower electrodescan be prevented.

Continuously, a remnant photo-resist is removed by a dry strip processusing O2/CF4/H2O/N2 or O2/N2 gas. A solvent liquid is used for removingby-products generated during the etching process and the remnantphoto-resist.

As a next step, a heat treatment process may be carried out to recover adeteriorated property of the lower electrode caused by the etchingprocess. At this time, another etching process using the BOE isaccompanied for a short time so as to remove impurities again beforeforming the dielectric layer.

In case of applying a MPS process to forming the lower electrode 154,the MPS is grown only on a inner face of the lower electrode 154 bycontrolling appropriate temperature and pressure conditions afterdepositing the poly-silicon. The CMP process is then carried out.

Even if not illustrated, a series of processes for forming the capacitorare eventually completed after forming the dielectric layer and an upperelectrode on the lower electrode 154.

FIG. 15 is a Transmission Electron Microscope (TEM) picture showing theleaning phenomenon of the lower electrodes after finishing the wetdip-out process.

(A) of FIG. 15 shows the pattern collapse of the lower electrodes inaccordance with the prior art.

(B) of FIG. 15 shows that the pattern collapse of the lower electrodesin accordance with the improved prior art.

As shown, the pattern collapse of the lower electrodes are still found.

(C) of FIG. 15 shows no pattern collapse of the lower electrodes inaccordance with the present invention.

FIG. 16 is a TEM picture illustrating a lower electrode pattern inaccordance with the improved prior and the present art.

As shown in (A), a bowing phenomenon of the lower electrodes indicatedwith a reference mark ‘160’ is generated to the lower electrodes. Also,a critical dimension 162 of the lower plane of the lower electrode issmaller than that of the upper plane of the lower electrode.

(B) of FIG. 16 shows that no bowing phenomenon is found and a criticaldimension 162 of the lower plane of the lower electrode is substantiallyimproved compared with that of the lower plane of the lower electrode.

As a result, not only the lifting phenomenon but also, the capacitanceof the lower electrode is substantially improved.

In conclusion, an improvement for preventing the bridge phenomenonoccurring between the lower electrodes and increasing the capacitance ofthe same is disclosed.

In addition, the paired lower electrodes are located at both sides ofthe bit line and disposed in the zigzag distribution. Consequently, thearea that the paired lower electrodes face each other in oppositedirection is reduced. As a result, the short of the paired lowerelectrode caused by the interfacial tension generated during performingthe wet dip-out process is prevented. Also, to reduce contactresistance, the paired lower electrodes are disposed in the zigzagdistribution or the contact pads are formed over the upper plane of thecapacitor plug.

1. A semiconductor device, comprising: a plurality of capacitor plugsformed within a predetermined interval interleaved between two bit linesand midpoints of capacitor plugs are located at inter-section points ofX axis virtual line and Y axis virtual line, wherein the X axis virtuallines are parallel with the bit lines and the Y axis virtual lines areperpendicular to the X axis virtual lines; and a plurality of lowerelectrodes of capacitors formed within a predetermined interval to berespectively connected with the capacitor plugs in one to onecorrespondence. each lower electrode being octagonally or circularlyshaped.
 2. The semiconductor device as recited in claim 1, wherein alower electrode and neighbored lower electrode disposed along adirection of Y virtual axis line are formed not to have overlapped area,if one of lower electrode is moved to same X virtual axis line as theother lower electrode.
 3. The semiconductor device as recited in claim1, wherein the lower electrode and neighbored lower electrode disposedalong a direction of Y virtual axis are not on the same Y virtual axis.4. The semiconductor device as recited in claim 1, wherein the midpointsof the lower electrode and the neighbored lower electrode are notdisposed along the same Y virtual axis.
 5. The semiconductor device asrecited in claim 1, wherein a ratio of a major axis to a minor axis ofthe upper plane of the lower electrodes ranges from about 1 to 1 toabout 2 to
 1. 6. The semiconductor device as recited in claim 1, whereinan area of an upper plane of the lower electrode is practicallyidentical to that of an lower plane of the lower electrode in view of athree-dimensional structure and the lower electrode features a octagonalor a circular cylinder structure having a lateral plane connecting theupper plane with the lower plane, wherein the lateral plane issubstantially vertical to the upper plane and lower plane respectively.7. A method for fabricating a semiconductor device, comprising: a)forming a plurality of capacitor plugs within a predetermined intervalinterleaved between two bit lines by arranging midpoints of capacitorplugs located at inter-section points of X axis virtual line and Y axisvirtual line, wherein the X axis virtual lines are parallel with the bitlines and the Y axis virtual lines are perpendicular to the X axisvirtual lines; and b) forming a plurality of lower electrodes ofcapacitors within a predetermined interval to be respectively connectedwith the capacitor plugs in one to one correspondence, each lowerelectrode being octagonally or circularly shaped.
 8. The method asrecited in claim 7, wherein an area of an upper plane of the lowerelectrode is practically identical to that of an lower plane of thelower electrode and the lower electrode has an octagonal or circularcylinder structure which has a lateral plane connecting the upper planewith the lower plane and practically vertical to the upper plane andlower plane.